This invention relates to a nonvolatile semiconductor memory device applied to an EEPROM or flash memory composed of electrically rewritable nonvolatile memory cells.
In recent years, electrically rewritable nonvolatile semiconductor memory devices have been put to practical use in the form of EEPROMs or flash memory devices. Especially, a NAND EEPROM where memory cells are connected in series to form NAND cells has been attracting because of its high integration.
The memory cells in the NAND EEPROM have an FETMOS structure where a floating gate (a charge storage layer) and a control gate are laid one on top of the other via an insulating film on a semiconductor substrate. The memory cells are connected in series in such a manner that adjacent cells share their source and drain, thereby forming NAND cells. The NAND cells are arranged in a matrix to construct a memory cell array. The drain at one end of a set of NAND cells arranged in one direction on the memory cell array is connected to a bit line via a select gate transistor and the source at the other end of the set is connected to a common source line via another select gate transistor.
This type of NAND EEPROM has been described in, for example, K. D. Suh, et al., "A 3.3-V 32-Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme," IEEE J. Solid-State Circuits, Vol. 30, Nov. 1995, pp. 1149-1156 or Y. Iwata, et al., "A 35-ns Cycle Time 3.3-V only 32-Mb NAND Flash EEPROM," IEEE J. Solid-State Circuits, Vol. 30, Nov. 1995, pp. 1157-1164.
The basic operation of this type of NAND EEPROM is as follows. A memory cell array is generally divided into blocks in units of word lines. For example, when 16 memory cells constitute a NAND cell, a memory cell array is divided into blocks in units of 16 word lines. This enables cells to be selected in blocks. To erase the data, all the word lines in the selected block are made 0V and an erase voltage of about 20V is applied to a p-type well in which the memory cell array has been formed. This permits the electrons in the floating gates of the memory cells to leak away to the substrate in a form of FN tunnel current. As a result, the threshold values of the memory cells in the selected block are brought into a negative erased state (e.g., data "0"). For the unselected blocks, the word lines are placed in a floating state, which raises the potential of the word lines through the capacitive coupling with the substrate, thereby preventing the data from being erased.
To read the data, 0V is applied to the selected word line and a pass voltage is applied to the unselected word lines. The pass voltage enables conduction even if the threshold values of the memory cells are positive (data "1"). In this state, data reading is done by sensing the conduction between the common source line and bit line. If a memory cell connected to the selected word line has data "0", conduction will be permitted between the common source line and bit line.
Data writing is done in the opposite voltage relations to those in data erasing. The p-type well is made 0V, a write voltage of about 20V is applied to the selected word line, and an intermediate voltage is applied to the unselected word lines. Depending on the potential applied to the bit line according to the data to be written, the channel potential is controlled in such a manner that electrons are injected from the channel into the floating gate in the case of "1" data and are prevented from being injected in the case of "0" data. The bit line with "1" data is made 0V and the data is transferred to the channel of the memory cell of the selected word line. As a result, a high voltage is applied between the selected word line and channel, which injects electrons into the floating gate of the memory cell. The bit line with "0" data is made Vcc. After the data has been transferred to the channel of the memory cell, the bit line is placed in the floating state. This permits the potential of the channel to rise further through the capacitive coupling with the word line, which prevents a high voltage from being applied between the selected word line and channel, thereby preventing electrons from being injected.
In data erasure where a high voltage is applied to the p-type well on which the entire memory cell array has been formed, erasing only the memory cells along one word line (this is usually called one page) is not effected, in general, because the other word lines are disturbed seriously. Methods of preventing the data from being erased in the unselected NAND blocks includes a method of applying the same high voltage as that of the p-type well to all the word lines of the unselected blocks and a method of keeping all the word lines of the unselected blocks in the floating state. With the latter method, the capacitive coupling with the p-type well brings all the word lines of the unselected blocks to a constant high potential, preventing the data from being erased.
After the data has been written or erased, verify reading is effected to verify whether the threshold values of the memory cells lie in a specific range.
As described earlier, in the conventional NAND EEPROM, the data is written in one word line (or in one page) and the data is erased in NAND blocks including 16 word lines in the case of 16-stage NAND cells. Therefore, for example, it is impossible to rewrite the data only in part of the memory cells of a word line in the same NAND block or to protect the flag bits for the data management from erasure.
To change the write page size or the erase page size, the number of memory cells connected to one word line is reduced to half, for example. To realize this, the number of row decoders for selecting and driving the word lines has to be doubled because the word lines are divided into two groups. For example, in the case of the existing 64-Mbit NAND EEPROM, the row decoder circuit accounts for 5.3% of the 123-mm.sup.2 chip size. To meet the above specifications, a 5.3% increase in the chip size is needed. If the word lines are divided into four groups or eight groups, the number of row decoders will increase accordingly, resulting in an increase in the chip size and a rise in the chip cost.
Conversely, when an attempt is made to keep the write page size or erase block size constant in order to manufacture a NAND EEPROM having a larger storage capacity, the chip is made long and narrow and thus unable to fit in the package, unless the number of the row decoders divided is increased.
The technique for dividing a memory cell array into two wells in the direction of word line and controlling the potential of the wells separately in order to write or erase the data of the memory cells connected to the selected word lines has been disclosed in, for example, Jpn. Pat. Appln. KOKAI Publication No. 4-360574. In this publication, nonvolatile semiconductor memory devices where memory cells are selected in units of block in the write/erase operation as in the NAND EEPROM described above have not been discussed and also the word lines of the unselected blocks have not been considered.